1. Field of the Invention
The present invention relates to integrated circuits and more particularly to circuits constructed in accordance with a CMOS technology, that is to say in which both n-channel and p-channel MOS transistors are incorporated on a single semiconductor substrate.
2. Description of the Prior Art
The CMOS technology is employed in particular for the implementation of logic functions and makes it possible in particular to obtain circuits which have low power consumption and operate at a very low voltage (of the order of a few volts).
However, it is sometimes desired to obtain a much higher blocking voltage capability than is permitted by the normal CMOS technology. This is the case, for example, with output stages for controlling special devices such as visual display devices which are supplied at a voltage of the order of one hundred volts.
MOS transistors which have improved blocking voltage capability and are thus capable of meeting the above-mentioned requirement have already been proposed. These transistors have a drain region which is not immediately adjacent to the channel region (namely the region covered by the control gate) but is separated from said channel region by a region having the same conductivity type as the drain region and a much lower dopant concentration. This region is of relatively substantial width (several microns for example between the heavily doped drain region and the channel region) and serves to carry part of the applied voltage by permitting an extension of the space charge towards the drain, said space charge being developed when the transistor is in the non-conducting state.
In the few known instances in which it has been endeavored up to the present time to fabricate both CMOS logic transistors and high-voltage MOS transistors on a single semiconductor substrate, the structures proposed in all cases are attended by a disadvantage in that they call for a relatively large number of fabrication steps and a large number of different masks.